4.3.1. Astable configuration

The figure below shows a simplified astable configuration of the 555 chip. In this configuration, the chip serves as an oscillator that produces accurate waveforms whose frequency can be controlled by adjusting the external RC circuit, as will be explained.

Figure 4‑9 Astable configuration
(Souce: referenced)

The explanation is based on the brilliant explanation of Mr.Charles Platt in the book Make: Electronics:

• Pin 1 is connected to the ground, and the Pin 8 is connected to VCC
• Pin 5 is not used and is hence grounded via capacitor C2 to eliminate noise
• Flip-flop is a sequential logic component that is able to preserve the state of one bit and whose work we will get to know later.  For now, it is important that we understand that it remembers the state
  • If the flip-flop is SET through S input, its Q output value 1 is sent to output pin 3. Also, its inverted Q output value 0 is sent to the base of the NPN transistor
  • If the flip-flop is RESET through R input, its Q output value 0 is sent to output pin 3. Also, its inverted Q output value 1 is sent to the base of the NPN transistor
• Comparators 1 and 2 compare voltages and are used to SET and RESET the flip-flop
  • The (+) input of comparator 1 is connected to 1/3 of the source voltage by the use of a voltage divider network and serves as a reference voltage. The (-) input of comparator 1 is connected to pin 2
  • The (-) input of comparator 2 is connected to 2/3 of the source voltage by the use of a voltage divider network and serves as a reference voltage. The (+) input of comparator 2 is connected to pin 6
• Pin 4 is used to reset the flip-flop with low input. It implicates the fact that it’s high input enables the flip-flop, so we tied it high on VCC in order to permanently enable the flip-flop
• Pin 7 is connected to the collector of the NPN transistor and it is used to discharge the capacitor C1 when the NPN transistor conducts
• Pin 6 is connected to pin 2 in order to trigger the chip with low input
• Pins 8, 7, and 6, together with R1 and R2 resistors and C1 capacitor form an RC circuit that will control the behavior of the astable configuration

Let us try to explain the workings of the astable configuration, by following the steps:

1. If the voltage value on pin 2 is below the 1/3 of the source voltage, the output of comparator 1 is high which sets the flip-flop
2. Consequently, the Q output value 1 from the flip-flop is sent to the output on pin 3 as a high value and the positive part of the cycle begins
3. At the same, the inverted Q output value 0 from the flip-flop is sent to the base of the NPN transistor and disconnects pin 7 from the ground
4. Since pin 7 is not grounded, the RC circuit is set in motion. Capacitor C1 starts to charge, at a rate determined by the resistance values R1 and R2, and the capacitance of capacitor C1
5. When the voltage on pin 6 is above the 2/3 of the source voltage, the output of comparator 2 is high which resets the flip-flop
6. Consequently, the Q output value 0 from the flip-flop is sent to the output as a low value and the negative part of the cycle begins
7. At the same, the inverted Q output value 1 from the flip-flop is sent to the base of the NPN transistor and connects pin 7 to the ground
8. Capacitor C1 starts to discharge through the R2 resistor all the way to input pin 2. When the voltage at input pin 2 falls below a value less than 1/3 of the source voltage, the chip is triggered again and the cycle is repeated

It is clear that we have produced a clock oscillator and that none of the states of the chip is permanent or stable. Hence, this configuration is called astable.

It is further important to note that we have two different RC circuits – one for charging, and the other for the discharging of the C1 capacitor. In other words, the first RC circuit defines the length of the positive part of the cycle and is constructed using R1, R2 resistors, and a C1 capacitor. The second RC circuit defines the length of the negative part of the cycle and is constructed using the R2 resistor and C1 capacitor. It is obvious that this results in an inequality in the times that the output has in states 1 and 0, which is clearly shown in the figure.

Figure 4‑10 Positive and negative cycles of astable configuration

To avoid this, we can reduce the influence of resistor R1 with a simple trick, by using the value of the R2 resistor much higher, so that the R1 resistor becomes insignificant.

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References:

https://www.electronics-tutorials.ws/waveforms/555_timer.html

C. Platt, Make Electronics (Maker Media, 2015)