To create a binary counter, we will use the knowledge gained so far about the operation of JK flip-flops and frequency division. If we observe the change of bits during the binary count 0 – 15 in the following figures, we can notice that the far-right bit changes its value with each clock. The bit on its left side changes the value by half frequency and that happens when the right bit changes the value from 1 to 0. Analogously for all left bits, each left bit changes its value by half the frequency of the right when changing the right bit from 1 to 0. These observations can be applied to connecting JK flip-flops, as shown in the figure. Inputs J and K are connected to the input voltage, so the output continuously toggles the state from 0 to 1 and vice versa, with the arrival of the clock. The clock is brought only to the first flip-flop, so it changes state with each clock. Each subsequent flip-flop is triggered by an inverted output, that is, when the previous flip-flop changes state from 1 to 0, just like in the figure.
(Source: referenced)
(Source: referenced)
This kind of architecture realizes asynchronous counters which, due to the propagation delay, have lower performance than synchronous ones. It is important to understand that every change of state requires some time. As the value of the previous flip-flop changes from 1 to 0, a clock is triggered that results in a change in the state of the next flip-flop, which also takes time. Thus, the delay is propagated from one flip-flop to another, which is called propagation delay. In synchronous counters, all flip-flops are triggered with the same clock, so they are faster because they do not suffer from propagation delay.
References:
https://www.allaboutcircuits.com/textbook/digital/chpt-11/asynchronous-counters/
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