The presented SR latches suffer from two shortcomings. The one that is evident, refers to the fact that we have a forbidden state of entry. Namely, the circuit must not be triggered by the S and R inputs at the same time. The next problem relates to our tendency to control the circuit, that is, to be able to fire it only at the desired moment. Therefore, in the next step, by upgrading the SR latch, we will achieve a JK flip-flop that solves both of these problems. The flip-flop, unlike the latch, contains a clock that we will use to trigger the assembly.
(Source: referenced)
We can notice that the inputs changed their names – S input became J and R input became K, according to the initials of Jack Kilby, the inventor of this circuit. Furthermore, inputs J and K are now connected to the clock, but also to the opposite outputs of the circuit. Why is that so? The connection to the clock will allow us to trigger the circuit at a discrete, desired moment. Furthermore, connecting the inputs to opposite circuit outputs completely eliminates the simultaneous possibility of circuit triggering because the outputs are inverse, and we know that all NAND inputs must be of value 1 for output to be 0 and thus trigger the circuit. Finally, if the inputs J and K are values ​​of 1 at the same time, the JK flip-flop will continuously change state from 0 to 1 and vice versa, each time the clock arrives, and this is called the toggle mode. This also solved the problem of the forbidden state of the SR latch. It is important to emphasize that the circuit is triggered by the edge of the clock, and not its entire length, which ensures proper operation. Namely, when the flip-flop is triggered along the entire length of the clock, there is a danger that the input signal could last shorter than the clock. In this case, the input signal representing the correct state would disappear before the clock, so the faulty state would be written to the circuit.
References:
https://commons.wikimedia.org/wiki/File:JK-FlipFlop_(4-NAND).PNG
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