5.2.1. SR latch

By connecting the NOR gates of the 7402 chip in the interesting way shown in the picture, we will achieve 1 memory bit, called an SR latch.

Figure 5‑4 NOR SR latch with truth table
(Source: referenced)

To understand the operation of the circuit, it is important to keep in mind that the output from the NOR gate is 1 only when both inputs are 0. Let’s start by bringing the value 1 to the S input. The output of the lower NOR gate must be 0 because one of its inputs is 1. Now 0 the output of the lower gate comes to the input of the upper NOR gate, and since R is input 0, the output of the upper gate must be 1. The output of the upper gate corresponds to Q output and the value is 1. The question arises, what will happen if we return the S input to the value 0? Since output 1 from the upper NOR gate comes to the input of the lower NOR gate, the output of the lower NOR gate will certainly be 0. So now it is irrelevant what the value of S input is because at least one input of the lower NOR gate is 1, which makes its output 0.

Analogous to the above analysis, let’s try to explain the opposite situation. If we bring the value 1 to the R input, the output from the upper NOR gate must be 0, because one of its inputs is 1. Now 0 the output of the upper gate comes to the input of the lower NOR gate, and since S input is 0, the output of the lower gate must be 1. The output of the lower gate corresponds to the Q inverted output and the value is 1. What will happen if we now return the R input to 0? Since output 1 from the lower NOR gate comes to the input of the upper NOR gate, the output of the upper NOR gate will certainly be 0. So now it is irrelevant what is the value of R input because at least one input of the upper NOR gate 1, makes its output 0. This ingenious invention of connecting logic gates enables the permanent storage of state.

It is interesting that an SR latch can be easily built from NAND circuits, but it has a negative logic. In other words, the S and R inputs must be 0 to trigger the circuit. So let’s build a new memory circuit, this time using a 7400 NAND chip.

Figure 5‑5 NAND SR latch with truth table
(Source: referenced)

Let us prove this with experiments.

References:

https://commons.wikimedia.org/wiki/File:SR-NOR-latch.png

https://commons.wikimedia.org/wiki/File:SR_Flip-flop_Diagram.svg

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