4.3.5. Bistable configuration

A bistable configuration is the simplest of configurations. We will get acquainted with the concept of bistable, or flip-flop in more detail later, but for now, it is enough to understand that bistable can permanently remember the state of one bit.

The figure below shows a simplified bistable configuration of the 555 chip.

Figure 4‑15 Bistable configuration
(Source: referenced)

The explanation is based on the brilliant explanation of Mr.Charles Platt in the book Make: Electronics:

• Pin 1 is connected to the ground, and the Pin 8 is connected to VCC
• Pin 5 is not used and is hence grounded via capacitor C2 to eliminate noise
• Pin 6 is not used and is hence grounded
• Pin 7 is not used in this configuration and is hence disconnected
• Flip-flop is a sequential logic component that is able to preserve the state of one bit and whose work we will get to know later.  For now, it is important that we understand that it remembers the state
  • If the flip-flop is SET through S input, its Q output value 1 is sent to output pin 3. Also, its inverted Q output value 0 is sent to the base of the NPN transistor
  • If the flip-flop is RESET through R input, its Q output value 0 is sent to output pin 3. Also, its inverted Q output value 1 is sent to the base of the NPN transistor
• Comparators 1 and 2 compare voltages and are used to SET and RESET the flip-flop
  • The (+) input of comparator 1 is connected to 1/3 of a source voltage by the use of a voltage divider network and serves as a reference voltage. The (-) input of comparator 1 is connected to pin 2
  • The (-) input of comparator 2 is connected to 2/3 of a source voltage by the use of a voltage divider network and serves as a reference voltage. The (+) input of comparator 2 is connected to pin 6
• Pin 2 is used as the trigger pin and uses a pull-up resistor in order to be connected to VCC since triggering is done with low-value input
• Pin 4 is used as the reset pin and uses a pull-up resistor in order to be connected to VCC since resetting is done with low-value input
• The top SPST switch is used to provide a low input value from the ground to trigger the chip on the pin 2
• The bottom SPST switch is used to provide a low input value from the ground to reset the chip on the pin 4

Let us try to explain the workings of the bistable configuration, by following the steps:

1. If the voltage value on pin 2 is below the 1/3 of the source voltage, the output of comparator 1 is high which sets the flip-flop. It will happen if we press the top SPST switch
2. Consequently, the Q output value 1 from the flip-flop is sent to the output on pin 3 as a high value and that value remains constant and stable after the SPST switch is released
3. If we press the bottom SPST switch, it will reset the flip-flop
4. Consequently, the Q output value 0 from the flip-flop is sent to the output on pin 3 as a low value and that value remains constant and stable after the SPST switch is released

It is important to notice that we have achieved to preserve the state of one bit, which will be explained in detail during realizing latches and flip-flops in the chapter that covers sequential circuits.

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References:

https://www.electronics-tutorials.ws/waveforms/555_timer.html

C. Platt, Make Electronics (Maker Media, 2015)