4.2. RAM realization

The realization of the ROM module follows below. (download pdf)

Figure 4‑3 RAM schematics

• U_ – X1 oscillator clock that provides U1 inverted CLK input is cut-off and exchanged with the slower one, realized with 555 chip (~1Hz), in order that we can inspect the work of the processor
• U9 – VCC, GND
• U9 – IO0-IO7 data pins are connected to A0-A7 pins of the data buffer U4 – in the same time, data pins are connected to LEDs to show the state
• U9 – A0-A14 address pins are connected to the pins of address buffers U2 (A0-A7) and U3 (A0-A6)
• U9 – inverted CS pin is connected to the output of the inverter gate U5B which input is taken from A15 bit of the address bus U3 (A7)
• U9 – inverted OE pin is connected to the inverted MREQ signal of the control buffer U6 to make sure that the RAM module active only in the case of the memory request
• U9 – inverted W pin is connected to the inverted WR signal of the control buffer U6

Figure 4‑4 RAM realization

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