2.3. NAND

The NAND logic gate requires both inputs to be 1 for the output to be 0. Analogously follows for three or more inputs.

Figure 2‑7 NAND transistor connection with truth table and expression

It is not difficult to understand that this is the inverted output of the AND gate. Also, it is convenient to note that the circuit is almost identical to the AND circuit, only its output is taken from the collector, not from the emitter. Voltage VCC will not appear on the collector output only if both transistors are in saturation.

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